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ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 low-noise, 8-channel, 24-bit analog front-end for biopotential measurements check for samples: ads1299 with its high levels of integration and exceptional 1 features performance, the ads1299 enables the creation of 23 ? eight low-noise pgas and eight high- scalable medical instrumentation systems at resolution simultaneous-sampling adcs significantly reduced size, power, and overall cost. ? very low input-referred noise: the ads1299 has a flexible input multiplexer per 1.0 v pp (70-hz bw) channel that can be independently connected to the ? low power: 5 mw/channel internally-generated signals for test, temperature, and lead-off detection. additionally, any configuration of ? input bias current: 300 pa input channels can be selected for derivation of the ? data rate: 250 sps to 16 ksps patient bias output signal. the ads1299 operates at ? cmrr: ? 110 db data rates from 250 sps to 16 ksps. lead-off detection can be implemented internal to the device, ? programmable gain: 1, 2, 4, 6, 8, 12, or 24 either with an external pull-up or pull-down resistor or ? unipolar or bipolar supplies: an excitation current sink or source. ? analog: 4.75 v to 5.25 v multiple ads1299 devices can be cascaded in high ? digital: 1.8 v to 3.6 v channel count systems in a daisy-chain configuration. ? built-in bias drive amplifier, the ads1299 is offered in a tqfp-64 package lead-off detection, test signals specified from ? 40 c to +85 c. ? built-in oscillator ? internal or external reference ? flexible power-down, standby mode ? pin-compatible with the ads1298ipag ? spi ? -compatible serial interface ? operating temperature range: ? 40 c to +85 c applications ? medical instrumentation (eeg and ecg) including: ? eeg, bispectral index (bis), evoked audio potential (eap), sleep study monitor ? high-precision, simultaneous, multichannel signal acquisition description the ads1299 is a low-noise, multichannel, simultaneous-sampling, 24-bit, delta-sigma ( ) analog-to-digital converter (adc) with a built-in programmable gain amplifier (pga), internal reference, and an onboard oscillator. the ads1299 incorporates all commonly-required features for electroencephalogram (eeg) applications. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 spi is a trademark of motorola. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. control clk gpio and control oscillator spi test signals and monitors spi patient bias and reference reference ref adc7 adc8 adc1 adc2 adc3 adc4 adc5 adc6 a7 a8 a1 a2 a3 a4 a5 a6 mux inputs ?? to channel
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. family and ordering information (1) operating number of maximum sample temperature product package option channels adc resolution rate (ksps) range ads1299ipag tqfp 8 24 16 ? 40 c to +85 c (1) for the most current package and ordering information, see the package option addendum at the end of this document, or visit the device product folder at www.ti.com . absolute maximum ratings (1) over operating free-air temperature range, unless otherwise noted. value unit avdd to avss ? 0.3 to +5.5 v dvdd to dgnd ? 0.3 to +3.9 v avss to dgnd ? 3 to +0.2 v v ref input to avss avss ? 0.3 to avdd + 0.3 v analog input to avss avss ? 0.3 to avdd + 0.3 v digital input voltage to dgnd ? 0.3 to dvdd + 0.3 v digital output voltage to dgnd ? 0.3 to dvdd + 0.3 v momentary 100 ma input current continuous 10 ma operating range, t a ? 40 to +85 c temperature storage range, t stg ? 60 to +150 c maximum junction, t j +150 c human body model (hbm) 1000 v electrostatic jedec standard 22, test method a114-c.01, all pins discharge (esd) charged device model (cdm) ratings 500 v jedec standard 22, test method c101, all pins (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 copyright ? 2012, texas instruments incorporated
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 electrical characteristics minimum and maximum specifications apply from ? 40 c to +85 c. typical specifications are at +25 c. all specifications are at dvdd = 3.3 v, avdd ? avss = 5 v, v ref = 4.5 v, external f clk = 2.048 mhz, data rate = 250 sps, and gain = 12, unless otherwise noted. ads1299 parameter test conditions min typ max unit analog inputs full-scale differential input voltage v ref / gain v (ainp ? ainn) see the input common-mode range input common-mode range subsection of the pga settings and input range section c i input capacitance 20 pf t a = +25 c, input = 2.5 v 300 pa i ib input bias current t a = ? 40 c to +85 c, input = 2.5 v 300 pa no lead-off 1000 m ? dc input impedance current source lead-off detection 500 m ? (i leadoff = 6 na) pga performance gain settings 1, 2, 4, 6, 8, 12, 24 bw bandwidth see table 5 adc performance resolution 24 bits dr data rate f clk = 2.048 mhz 250 16000 sps channel performance (dc performance) 10 seconds of data, gain = 24 (1) 1.0 v pp 250 points, 1 second of data, gain = 24, 1.0 1.35 v pp t a = +25 c input-referred noise (0.01 hz to 70 hz) 250 points, 1 second of data, gain = 24, 1.0 1.6 v pp t a = ? 40 c to +85 c all other sample rates and gain settings see noise measurements section inl integral nonlinearity full-scale with gain = 12, best fit 8 ppm e o offset error 60 v offset error drift 80 nv/ c e g gain error excluding voltage reference error 0.1 0.5 % of fs gain drift excluding voltage reference drift 3 ppm/ c gain match between channels 0.2 % of fs channel performance (ac performance) cmrr common-mode rejection ratio f cm = 50 hz and 60 hz (2) ? 110 ? 120 db psrr power-supply rejection ratio f ps = 50 hz and 60 hz 96 db crosstalk f in = 50 hz and 60 hz ? 110 db snr signal-to-noise ratio v in = ? 2 dbfs, f in = 10-hz input, gain = 12 121 db thd total harmonic distortion v in = ? 0.5 dbfs, f in = 10 hz ? 99 db (1) noise data measured in a 10-second interval. test not performed in production. input-referred noise is calculated with the input shorted (without electrode resistance) over a 10-second interval. (2) cmrr is measured with a common-mode signal of avss + 0.3 v to avdd ? 0.3 v. the values indicated are the minimum of the eight channels. copyright ? 2012, texas instruments incorporated 3
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com electrical characteristics (continued) minimum and maximum specifications apply from ? 40 c to +85 c. typical specifications are at +25 c. all specifications are at dvdd = 3.3 v, avdd ? avss = 5 v, v ref = 4.5 v, external f clk = 2.048 mhz, data rate = 250 sps, and gain = 12, unless otherwise noted. ads1299 parameter test conditions min typ max unit patient bias amplifier integrated noise bw = 150 hz 2 v rms gbp gain bandwidth product 50 k ? || 10 pf load, gain = 1 100 khz sr slew rate 50 k ? || 10 pf load, gain = 1 0.07 v/ s thd total harmonic distortion f in = 10 hz, gain = 1 ? 80 db cmir common-mode input range avss + 0.3 avdd ? 0.3 v i sc short-circuit current 1.1 ma quiescent power consumption 20 a lead-off detect 0, f dr / 4 continuous hz see register map section for settings frequency one time or periodic 7.8, 31.2 hz ilead_off[1:0] = 00 6 na ilead_off[1:0] = 01 24 na current ilead_off[1:0] = 10 6 a ilead_off[1:0] = 11 24 a current accuracy 20 % comparator threshold accuracy 30 mv external reference v i(ref) reference input voltage 5-v supply, v ref = (vrefp ? vrefn) 4.5 v vrefn negative input avss v vrefp positive input avss + 4.5 v input impedance 5.6 k ? internal reference v o output voltage 4.5 v v ref accuracy 0.2 % drift t a = ? 40 c to +85 c 35 ppm start-up time 150 ms system monitors analog supply 2 % reading error digital supply 2 % from power-up to drdy low 150 ms device wake up standby mode 31.25 s voltage t a = +25 c 145 mv temperature sensor reading coefficient 490 v/ c signal frequency see register map section for settings hz f clk / 2 21 , f clk / 2 20 test signal signal voltage see register map section for settings 1, 2 mv accuracy 2 % 4 copyright ? 2012, texas instruments incorporated
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 electrical characteristics (continued) minimum and maximum specifications apply from ? 40 c to +85 c. typical specifications are at +25 c. all specifications are at dvdd = 3.3 v, avdd ? avss = 5 v, v ref = 4.5 v, external f clk = 2.048 mhz, data rate = 250 sps, and gain = 12, unless otherwise noted. ads1299 parameter test conditions min typ max unit clock internal oscillator clock frequency nominal frequency 2.048 mhz t a = +25 c 0.5 % internal clock accuracy ? 40 c t a +85 c 2.5 % internal oscillator start-up time 20 s internal oscillator power consumption 120 w external clock input frequency clksel pin = 0 1.5 2.048 2.25 mhz digital input/output (dvdd = 1.8 v to 3.6 v) v ih high 0.8 dvdd dvdd + 0.1 v logic level, input voltage v il low ? 0.1 0.2 dvdd v v oh high i oh = ? 500 a 0.9 dvdd v logic level, output voltage v ol low i ol = +500 a 0.1 dvdd v i in input current 0 v < v digitalinput < dvdd ? 10 +10 a power-supply requirements analog supply (avdd ? avss) 4.75 5 5.25 v dvdd digital supply 1.8 1.8 3.6 v avdd ? dvdd ? 2.1 3.6 v supply current (bias turned off) i avdd avdd ? avss = 5 v 7.14 ma normal mode dvdd = 3.3 v 1 ma i dvdd dvdd = 1.8 v 0.5 ma power dissipation (analog supply = 5 v, bias amplifiers turned off) normal mode 39 42 mw quiescent power dissipation power-down 10 w standby mode, internal reference 5.1 mw quiescent power dissipation, normal mode 4.3 mw per channel temperature specified ? 40 +85 c temperature operating ? 40 +85 c range storage ? 60 +150 c thermal information ads1299 thermal metric (1) pag units 64 pins ja junction-to-ambient thermal resistance 43.3 jctop junction-to-case (top) thermal resistance 36.5 jb junction-to-board thermal resistance 60.6 c/w jt junction-to-top characterization parameter 0.1 jb junction-to-board characterization parameter 19.5 jcbot junction-to-case (bottom) thermal resistance n/a (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . copyright ? 2012, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com parametric measurement information noise measurements the ads1299 noise performance can be optimized by adjusting the data rate and pga setting. when averaging is increased by reducing the data rate, the noise drops correspondingly. increasing the pga value reduces the input-referred noise, which is particularly useful when measuring low-level biopotential signals. table 1 to table 4 summarize the ads1299 noise performance with a 5-v analog power supply. the data are representative of typical noise performance at t a = +25 c. the data shown are the result of averaging the readings from multiple devices and are measured with the inputs shorted together. a minimum of 1000 consecutive readings are used to calculate the rms and peak-to-peak noise for each reading. for the lower data rates, the ratio is approximately 6.6. table 1 shows measurements taken with an internal reference. the data are also representative of the ads1299 noise performance when using a low-noise external reference such as the ref5025 . table 1. input-referred noise ( v rms / v pp ) in normal mode 5-v analog supply and 4.5-v reference (1) pga pga gain = 1 gain = 2 dr bits of output noise- noise- config1 data rate ? 3-db free free register (sps) bandwidth (hz) v rms v pp snr (db) bits enob v rms v pp snr (db) bits enob 000 16000 4193 21.70 151.89 103.3 15.85 17.16 10.85 75.94 103.3 15.85 17.16 001 8000 2096 6.93 48.53 113.2 17.50 18.81 3.65 25.52 112.8 17.43 18.74 010 4000 1048 4.33 30.34 117.3 18.18 19.49 2.28 15.95 116.9 18.11 19.41 011 2000 524 3.06 21.45 120.3 18.68 19.99 1.61 11.29 119.9 18.60 19.91 100 1000 262 2.17 15.17 123.3 19.18 20.49 1.14 7.98 122.9 19.10 20.41 101 500 131 1.53 10.73 126.3 19.68 20.99 0.81 5.65 125.9 19.60 20.91 110 250 65 1.08 7.59 129.3 20.18 21.48 0.57 3.99 128.9 20.10 21.41 111 n/a n/a ? ? ? ? ? ? ? ? ? ? (1) at least 1000 consecutive readings were used to calculate the rms and peak-to-peak noise values in this table. table 2. input-referred noise ( v rms / v pp ) in normal mode 5-v analog supply and 4.5-v reference (1) pga pga gain = 4 gain = 6 dr bits of output noise- noise- config1 data rate ? 3-db free free register (sps) bandwidth (hz) v rms v pp snr (db) bits enob v rms v pp snr (db) bits enob 000 16000 4193 5.60 39.23 103.0 15.81 17.12 3.87 27.10 102.7 15.76 17.06 001 8000 2096 1.98 13.87 112.1 17.31 18.62 1.31 9.19 112.1 17.32 18.62 010 4000 1048 1.24 8.66 116.1 17.99 19.29 0.93 6.50 115.1 17.82 19.12 011 2000 524 0.88 6.13 119.2 18.49 19.79 0.66 4.60 118.1 18.32 19.62 100 1000 262 0.62 4.34 122.2 18.99 20.29 0.46 3.25 121.1 18.81 20.12 101 500 131 0.44 3.07 125.2 19.49 20.79 0.33 2.30 124.1 19.31 20.62 110 250 65 0.31 2.16 128.2 19.99 21.30 0.23 1.62 127.2 19.82 21.13 111 n/a n/a ? ? ? ? ? ? ? ? ? ? (1) at least 1000 consecutive readings were used to calculate the rms and peak-to-peak noise values in this table. 6 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 table 3. input-referred noise ( v rms / v pp ) in normal mode 5-v analog supply and 4.5-v reference (1) pga pga gain = 8 gain = 12 dr bits of output noise- noise- config1 data rate ? 3-db free free register (sps) bandwidth (hz) v rms v pp snr (db) bits enob v rms v pp snr (db) bits enob 000 16000 4193 3.05 21.32 102.3 15.69 16.99 2.27 15.89 101.3 15.53 16.83 001 8000 2096 1.11 7.80 111.0 17.14 18.45 0.92 6.41 109.2 16.84 18.14 010 4000 1048 0.79 5.52 114.0 17.64 18.95 0.65 4.53 112.2 17.34 18.64 011 2000 524 0.56 3.90 117.1 18.14 19.44 0.46 3.20 115.2 17.84 19.14 100 1000 262 0.39 2.76 120.1 18.64 19.94 0.32 2.26 118.3 18.34 19.65 101 500 131 0.28 1.95 123.1 19.14 20.44 0.23 1.61 121.2 18.83 20.14 110 250 65 0.20 1.38 126.1 19.64 20.95 0.16 1.13 124.3 19.34 20.65 111 n/a n/a ? ? ? ? ? ? ? ? ? ? (1) at least 1000 consecutive readings were used to calculate the rms and peak-to-peak noise values in this table. table 4. input-referred noise ( v rms / v pp ) in normal mode 5-v analog supply and 4.5-v reference (1) pga gain = 24 dr bits of output noise- config1 data rate ? 3-db free register (sps) bandwidth (hz) v rms v pp snr (db) bits enob 000 16000 4193 1.66 11.64 98.0 14.98 16.28 001 8000 2096 0.80 5.57 104.4 16.04 17.35 010 4000 1048 0.56 3.94 107.4 16.54 17.84 011 2000 524 0.40 2.79 110.4 17.04 18.35 100 1000 262 0.28 1.97 113.5 17.54 18.85 101 500 131 0.20 1.39 116.5 18.04 19.35 110 250 65 0.14 0.98 119.5 18.54 19.85 111 n/a n/a ? ? ? ? ? (1) at least 1000 consecutive readings were used to calculate the rms and peak-to-peak noise values in this table. copyright ? 2012, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com timing characteristics note: spi settings are cpol = 0 and cpha = 1. figure 1. serial interface timing figure 2. daisy-chain interface timing timing requirements for figure 1 and figure 2 (1) 2.7 v dvdd 3.6 v 1.8 v dvdd 2 v parameter description min typ max min typ max unit t clk master clock period 444 666 444 666 ns t cssc cs low to first sclk, setup time 6 17 ns t sclk sclk period 50 66.6 ns t spwh, l sclk pulse width, high and low 15 25 ns t dist din valid to sclk falling edge: setup time 10 10 ns t dihd valid din after sclk falling edge: hold time 10 11 ns t dohd sclk falling edge to invalid dout: hold time 10 10 ns t dopd sclk rising edge to dout valid: setup time 17 32 ns t csh cs high pulse 2 2 t clks t csdod cs low to dout driven 10 20 ns t sccs eighth sclk falling edge to cs high 4 4 t clks t sdecode command decode time 4 4 t clks t csdoz cs high to dout hi-z 10 20 ns t disck2st valid daisy_in to sclk rising edge: setup time 10 10 ns t disck2ht valid daisy_in after sclk rising edge: hold time 10 10 ns (1) specifications apply from ? 40 c to +85 c. load on d out = 20 pf || 100 k . 8 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 d isy_in a dout sclk msb d1 t disck2st msb 2 1 3 216 217 218 msb d1 lsb t disck2ht lsb d1 219 1 cs sclk din dout 2 3 8 1 2 8 3 t cssc t dist t dihd t dohd t csh t dopd t spwh t spwl t sccs hi-z t csdoz t csdod hi-z t sclk t sdecode clk t clk
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 pin configuration pag package tqfp-64 (top view) pin assignments name terminal function description avdd 19, 21, 22, 56 supply analog supply avdd 59 supply charge pump analog supply avdd1 54 supply analog supply avss 20, 23, 32, 57 supply analog ground avss 58 supply charge pump analog ground avss1 53 supply analog ground biasin 62 analog input bias drive input to mux biasinv 61 analog input/output bias drive inverting input biasout 63 analog output bias drive output biasref 60 analog input bias drive noninverting input cs 39 digital input spi chip select; active low clk 37 digital input master clock input clksel 52 digital input master clock select daisy_in 41 digital input daisy-chain input dgnd 33, 49, 51 supply digital ground din 34 digital input spi data in dout 43 digital output spi data out drdy 47 digital output data ready; active low copyright ? 2012, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads1299 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dvddgpio4 gpio3 gpio2 dout gpio1 daisy_in sclk start clk din dgnd drdy cs reset pwdn 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 in8n in8p in7n in7p in6n in6p in5n in5p in4n in4p in3n in3p in2n in2p in1n in1p reservedbiasout biasin biasinv biasref avdd avss avss avdd vcap3 avdd1 avss1 clksel dgnd dvdd dgnd srb1 2 avdd avss avdd avdd avss vrefp vrefn vcap4 nc vcap1 nc vcap2resv1 avss srb 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com pin assignments (continued) name terminal function description dvdd 48, 50 supply digital power supply gpio1 42 digital input/output general-purpose input/output pin gpio2 44 digital input/output general-purpose input/output pin gpio3 45 digital input/output gpio3 in normal mode gpio4 46 digital input/output gpio4 in normal mode in1n (1) 15 analog input differential analog negative input 1 in1p 16 analog input differential analog positive input 1 in2n 13 analog input differential analog negative input 2 in2p 14 analog input differential analog positive input 2 in3n 11 analog input differential analog negative input 3 in3p 12 analog input differential analog positive input 3 in4n 9 analog input differential analog negative input 4 in4p 10 analog input differential analog positive input 4 in5n 7 analog input differential analog negative input 5 in5p 8 analog input differential analog positive input 5 in6n 5 analog input differential analog negative input 6 in6p 6 analog input differential analog positive input 6 in7n 3 analog input differential analog negative input 7 in7p 4 analog input differential analog positive input 7 in8n 1 analog input differential analog negative input 8 in8p 2 analog input differential analog positive input 8 nc 27, 29 ? no connection reserved 64 analog output leave as open circuit reset 36 digital input system reset; active low resv1 31 digital input reserved for future use. must tie to logic low (dgnd) sclk 40 digital input spi clock srb1 17 analog input/output patient stimulus, reference, and bias signal 1 srb2 18 analog input/output patient stimulus, reference, and bias signal 2 start 38 digital input start conversion pwdn 35 digital input power-down; active low vcap1 28 ? analog bypass capacitor vcap2 30 ? analog bypass capacitor vcap3 55 analog analog bypass capacitor vcap4 26 analog output analog bypass capacitor vrefn 25 analog input negative reference voltage vrefp 24 analog input/output positive reference voltage (1) connect unused analog inputs in1x to in8x to avdd. 10 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 typical characteristics all plots are at t a = +25 c, avdd = 5 v, avss = 0 v, dvdd = 3.3 v, internal vrefp = 4.5 v, vrefn = avss, external clock = 2.048 mhz, data rate = 250 sps, and gain = 12, unless otherwise noted. input-referred noise noise histogram figure 3. figure 4. common-mode rejection ratio vs frequency leakage current vs input voltage figure 5. figure 6. leakage current vs temperature psrr vs frequency figure 7. figure 8. copyright ? 2012, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads1299 ?0.5?0.4 ?0.3 ?0.2 ?0.1 0 0.10.2 0.3 0.4 0.5 ?0.5?0.4 ?0.3 ?0.2 ?0.1 0 0.10.2 0.3 0.4 0.5 0 100 200 300 400 500 600 700 800 input?referred noise (v) occurences gain = 24 g004 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1 2 3 4 5 6 7 8 9 10 time (s) input?referred noise (v) gain = 24 g003 0 25 50 75 100 125 150 175 200 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 temperature (c) leakage current (pa) input voltage = 2.5 vdata rate = 250 sps to 8 ksps g007 80 85 90 95 100 105 110 115 120 10 100 1000 frequency (hz) power?supply rejection ratio (db) g = 1g = 2 g = 4 g = 6g = 8 g = 12 g = 24 g008 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?100 10 100 1000 frequency (hz) cmrr (db) gain = 1gain = 2 gain = 4 gain = 6 gain = 8 gain = 12 gain = 24 data rate = 4 kspsa in = avdd ? 0.3 v to avss + 0.3 v g005 0 50 100 150 200 250 300 350 400 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 input voltage (v) input leakage current (pa) data rate = 250 sps to 8 ksps data rate = 16 ksps g006
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com typical characteristics (continued) all plots are at t a = +25 c, avdd = 5 v, avss = 0 v, dvdd = 3.3 v, internal vrefp = 4.5 v, vrefn = avss, external clock = 2.048 mhz, data rate = 250 sps, and gain = 12, unless otherwise noted. thd vs frequency inl vs pga gain figure 9. figure 10. thd fft plot inl vs temperature (60-hz signal) figure 11. figure 12. fft plot offset vs pga gain (60-hz signal) (absolute value) figure 13. figure 14. 12 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2000 4000 6000 8000 frequency (hz) amplitude (dbfs) pga gain = 12thd = ?94 db snr = 101 db data rate = 16 ksps g013 0 100 200 300 400 500 600 1 10 30 pga gain offset (v) g014 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1 input range (normalized to full?scale) integral nonlinearity (ppm) +25c?40c +85c gain = 12 g011 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 frequency (hz) amplitude (dbfs) pga gain = 12thd = ?99 db snr = 120 db data rate = 500 sps g012 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 10 100 1000 frequency (hz) total harmonic distortion (db) gain = 1 gain = 2 gain = 4 gain = 6 gain = 8 gain = 12 gain = 24 data rate = 8 kspsa in = ?0.5 dbfs g009 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1 input (normalized to full-scale) integral nonlinearity (ppm) gain = 1gain = 2 gain = 4 gain = 6 gain = 8 gain = 12 gain = 24 g010
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 typical characteristics (continued) all plots are at t a = +25 c, avdd = 5 v, avss = 0 v, dvdd = 3.3 v, internal vrefp = 4.5 v, vrefn = avss, external clock = 2.048 mhz, data rate = 250 sps, and gain = 12, unless otherwise noted. test signal amplitude accuracy lead-off comparator threshold accuracy figure 15. figure 16. lead-off current source accuracy distribution figure 17. copyright ? 2012, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads1299 ?3.5 ?3 ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 ?3.5 ?3 ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 0 50 100 150 200 250 300 350 error in current magnitude (na) number of bins current setting = 24 na g017 7060 50 40 30 20 10 0 - 0.53 error (%) number of bins - 0.41 - 0.18 0.06 0.3 0.54 0.66 0.42 0.18 - 0.06 - 0.29 data from 31 devices, two lots g015 8070 60 50 40 30 20 10 0 - 20 threshold error (mv) number of bins - 15 0 1020 30 35 25 15 5 - 10 data from 31 devices, two lots g016
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com overview the ads1299 is a low-noise, low-power, multichannel, simultaneously-sampling, 24-bit, delta-sigma ( ) analog- to-digital converter (adc) with an integrated programmable gain amplifier (pga). this device integrates various eeg-specific functions that makes it well-suited for scalable electroencephalography (eeg) applications. the device can also be used in high-performance, multichannel, data acquisition systems by powering down the eeg-specific circuitry. the ads1299 has a highly-programmable multiplexer that allows for temperature, supply, input short, and bias measurements. additionally, the multiplexer allows any input electrodes to be programmed as the patient reference drive. the pga gain can be chosen from one of seven settings (1, 2, 4, 6, 8, 12, and 24). the adcs in the device offer data rates from 250 sps to 16 ksps. communication to the device is accomplished using an spi-compatible interface. the device provides four general-purpose input/output (gpio) pins for general use. multiple devices can be synchronized using the start pin. the internal reference can be programmed to 4.5 v. the internal oscillator generates a 2.048-mhz clock. the versatile patient bias drive block allows the average of any electrode combination to be chosen in order to generate the patient drive signal. lead-off detection can be accomplished by using a current source or sink. a one-time, in-band, lead-off option and a continuous, out-of-band, internal lead-off option are available. refer to figure 18 for a block diagram. 14 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 figure 18. functional block diagram copyright ? 2012, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads1299 drdy clk clksel start mux oscillator power-supply signal spi dvdd dgnd bias inv bias out bias ref lead-off excitation source gpio1gpio4 gpio3 cs sclk dindout gpio2 in8p in8n in7p in7n in6p in6n in5p in5n in4p in4n in3p in3n in2p in2n in1p in1n low-noise pga1 ds adc1 temperature sensor input bias amplifier reference vrefp vrefn control pwdn reset ds adc2 ds adc3 ds adc4 ds adc5 ds adc6 ds adc7 ds adc8 avdd avdd1 avss avss1 test signal biasin srb2 srb1 low-noise pga8 low-noise pga7 low-noise pga6 low-noise pga5 low-noise pga4 low-noise pga3 low-noise pga2
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com theory of operation this section contains details of the ads1299 internal functional elements. the analog blocks are discussed first, followed by the digital interface. blocks implementing eeg-specific functions are covered at the end of this document. throughout this document, f clk denotes the clk pin signal frequency, t clk denotes the clk pin signal period, f dr denotes the output data rate, t dr denotes the output data time period, and f mod denotes the frequency at which the modulator samples the input. input multiplexer the ads1299 input multiplexers are very flexible and provide many configurable signal-switching options. figure 19 shows the multiplexer on a single channel of the device. note that the device has eight such blocks, one for each channel. srb1, srb2, and biasin are common to all eight blocks. vinp and vinn are separate for each of the eight blocks. this flexibility allows for significant device and sub-system diagnostics, calibration, and configuration. switch setting selections for each channel are made by writing the appropriate values to the chnset[3:0] register (see the chnset: individual channel settings section for details) by writing the bias_meas bit in the config3 register and the srb1 bit in the misc1 register (see the config3: configuration register 3 subsection of the register map section for details). refer to the input multiplexer subsection of the eeg-specifc functions section for further information regarding the eeg-specific features of the multiplexer. (1) main is equal to either mux[2:0] = 000, mux[2:0] = 110, or mux[2:0] = 111. figure 19. input multiplexer block for one channel 16 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 mux[2:0] = 101 tempp mux[2:0] = 100 mvddp mux[2:0] = 011 from loffp main (1) mux[2:0] = 110 mux[2:0] = 001 to pgap to pgan mux[2:0] = 001 mux[2:0] = 111 vinp vinn main (1) and srb1 from loffn (avdd+avss) 2 mvddn tempn device mux int_test (vrefp + vrefn) 2 testp int_test testm srb2 bias_in to next channels chxset[3] = 1 srb1 to next channels main (1) and srb1 mux[2:0] = 010 and bias_meas mux[2:0] = 010 and bias_meas biasref_int=1 biasref_int=0 mux[2:0] = 100 mux[2:0] = 011 mux[2:0] = 101 biasref
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 device noise measurements setting chnset[2:0] = 001 sets the common-mode voltage of [(vrefp + vrefn) / 2] to both channel inputs. this setting can be used to test inherent device noise in the user system. test signals (testp and testn) setting chnset[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power- up. this functionality allows the device internal signal chain to be tested out. test signals are controlled through register settings (see the config2: configuration register 2 subsection in the register map section for details). test_amp controls the signal amplitude and test_freq controls switching at the required frequency. temperature sensor (tempp, tempn) the ads1299 contains an on-chip temperature sensor. this sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in figure 20 . the difference in diode current densities yields a voltage difference proportional to absolute temperature. as a result of the low thermal resistance of the package to the printed circuit board (pcb), the internal device temperature tracks pcb temperature closely. note that self-heating of the ads1299 causes a higher reading than the temperature of the surrounding pcb. the scale factor of equation 1 converts the temperature reading to degrees celsius. before using this equation, the temperature reading code must first be scaled to microvolts. (1) figure 20. temperature sensor measurement in the input supply measurements (mvddp, mvddn) setting chnset[2:0] = 011 sets the channel inputs to different supply voltages of the device. for channels 1, 2, 5, 6, 7, and 8, (mvddp ? mvddn) is [0.5 (avdd + avss)]; for channels 3 and 4, (mvddp ? mvddn) is dvdd / 4. note that to avoid saturating the pga while measuring power supplies, the gain must be set to '1'. lead-off excitation signals (loffp, loffn) the lead-off excitation signals are fed into the multiplexer before the switches. the comparators that detect the lead-off condition are also connected to the multiplexer block before the switches. for a detailed description of the lead-off block, refer to the lead-off detection subsection in the eeg-specific functions section. copyright ? 2012, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads1299 2x 1x 1x 8x avdd avss temperature sensor monitor to mux tempp to mux tempn temperature ( c) = temperature reading ( v) 145,300 v m - m 490 v/ c m + 25 c
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com auxiliary single-ended input the biasin pin is primarily used for routing the bias signal to any electrodes in case the bias electrode falls off. however, the biasin pin can be used as a multiple single-ended input channel. the signal at the biasin pin can be measured with respect to the voltage at the biasref pin using any of the eight channels. this measurement is done by setting the channel multiplexer setting to '010' and the bias_meas bit of the config3 register to '1'. analog input the ads1299 analog input is fully differential. assuming pga = 1, the input (inp ? inn) can span between ? v ref to +v ref . refer to table 7 for an explanation of the correlation between the analog input and digital codes. there are two general methods of driving the ads1299 analog input: single-ended or differential (as shown in figure 21 and figure 22 , respectively). note that inp and inn are 180 c out-of-phase in the differential input method. when the input is single-ended, the inn input is held at the common-mode voltage, preferably at mid- supply. the inp input swings around the same common voltage and the peak-to-peak amplitude is (common- mode + 1/2 v ref ) and (common-mode ? 1/2 v ref ). when the input is differential, the common-mode is given by [(inp + inn) / 2]. both inp and inn inputs swing from (common-mode + 1/2 v ref ) to (common-mode ? 1/2 v ref ). for optimal performance, the ads1299 is recommended to be used in a differential configuration. figure 21. methods of driving the ads1299: single-ended or differential figure 22. using the ads1299 in single-ended and differential input modes 18 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 cm + 1/2 v ref +1/2 v ref - v ref 1/2 single-ended inputs t inp cm voltage cm v - ref 1/2 cm + 1/2 v ref differential inputs t inp inn cm voltage cm 1/2 v ref - +v ref - v ref common-mode voltage (differential mode) = 2 , common-mode voltage (single-ended mode) = inn. inn = cm voltage input range (differential mode) = (ainp ainn) = v ( v ) = 2 v . - ref ref - - ref (inp) + (inn) device - v to +1/2 v 1/2 ref ref common voltage single-ended input device vpeak-to-peak ref vpeak-to-peak ref common voltage differential input
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 pga settings and input range the low-noise pga is a differential input and output amplifier, as shown in figure 23 . the pga has seven gain settings (1, 2, 4, 6, 8, 12, and 24) that can be set by writing to the chnset register (see the chnset: individual channel settings subsection of the register map section for details). the ads1299 has cmos inputs and therefore has negligible current noise. table 5 shows the typical bandwidth values for various gain settings. note that table 5 shows small-signal bandwidth. for large signals, performance is limited by pga slew rate. figure 23. pga implementation table 5. pga gain versus bandwidth nominal bandwidth at room gain temperature (khz) 1 662 2 332 4 165 6 110 8 83 12 55 24 27 the pga resistor string that implements the gain has 39.6 k ? of resistance for a gain of 12. this resistance provides a current path across the pga outputs in the presence of a differential input signal. this current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input. copyright ? 2012, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads1299 low-noise pgap r18.15 k w 2 r3.3 k (for gain = 12) w 1 r18.15 k w 2 from muxp low-noise pgan from muxn to adc
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com input common-mode range the usable input common-mode range of the front-end depends on various parameters, including the maximum differential input signal, supply voltage, pga gain, and so forth. this range is described in equation 2 : where: v max_diff = maximum differential signal at the pga input cm = common-mode range (2) for example: if v dd = 5 v, gain = 12, and v max_diff = 350 mv then 2.3 v < cm < 2.7 v input differential dynamic range the differential (inp ? inn) signal range depends on the analog supply and reference used in the system. this range is shown in equation 3 . (3) the 5-v supply, with a reference of 4.5 v and a gain of 12 for eegs, is optimized for power with a differential input signal of approximately 300 mv. adc modulator each ads1299 channel has a 24-bit, adc. this converter uses a second-order modulator optimized for low- noise applications. the modulator samples the input signal at the rate of (f mod = f clk / 2). as in the case of any modulator, the ads1299 noise is shaped until f mod / 2, as shown in figure 24 . the on-chip digital decimation filters explained in the next section can be used to filter out the noise at higher frequencies. these on-chip decimation filters also provide antialias filtering. this converter feature drastically reduces the complexity of the analog antialiasing filters typically required with nyquist adcs. figure 24. modulator noise spectrum up to 0.5 f mod 20 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 normalized frequency (f in /f mod ) power spectral density (db) g001 max (inp inn) < - v ref gain full-scale range = v ref gain ; = 2 v ref gain avdd 0.2 - - gain v max_diff 2 > cm > avss + 0.2 + gain v max_diff 2
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 digital decimation filter the digital filter receives the modulator output and decimates the data stream. by adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for higher data rates. higher data rates are typically used in eeg applications for ac lead-off detection. the digital filter on each channel consists of a third-order sinc filter. the sinc filter decimation ratio can be adjusted by the dr bits in the config1 register (see the register map section for details). this setting is a global setting that affects all channels and, therefore, all channels operate at the same data rate in a device. sinc filter stage (sinx / x) the sinc filter is a variable decimation rate, third-order, low-pass filter. data are supplied to this section of the filter from the modulator at the rate of f mod . the sinc filter attenuates the modulator high-frequency noise, then decimates the data stream into parallel data. the decimation rate affects the overall converter data rate. equation 4 shows the scaled z-domain transfer function of the sinc filter. (4) the frequency domain transfer function of the sinc filter is shown in equation 5 . where: n = decimation ratio (5) copyright ? 2012, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads1299 ? h(z) = ? 3 1 z - - n 1 z - - 1 ? h(f) = ? 3 sin n f p f mod n sin p f f mod
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com the sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. at these frequencies, the filter has infinite attenuation. figure 25 shows the sinc filter frequency response and figure 26 shows the sinc filter roll-off. with a step change at input, the filter takes 3 t dr to settle. after a rising edge of the start signal, the filter takes t settle time to give the first data output. the settling time of the filters at various data rates are discussed in the start subsection of the spi interface section. figure 27 and figure 28 show the filter transfer function until f mod / 2 and f mod / 16, respectively, at different data rates. figure 29 shows the transfer function extended until 4 f mod . the ads1299 pass band repeats itself at every f mod . the input r-c antialiasing filters in the system should be chosen such that any interference in frequencies around multiples of f mod are attenuated sufficiently. figure 25. sinc filter frequency response figure 26. sinc filter roll-off figure 27. transfer function of on-chip figure 28. transfer function of on-chip decimation filters until f mod / 2 decimation filters until f mod / 16 22 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 normalized frequency (f in /f mod ) gain (db) dr[2:0] = 000dr[2:0] = 001 dr[2:0] = 010 dr[2:0] = 011 dr[2:0] = 100dr[2:0] = 101 dr[2:0] = 110 g027 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 normalized frequency (f in /f mod ) gain (db) dr[2:0] = 000dr[2:0] = 001 dr[2:0] = 010 dr[2:0] = 011 dr[2:0] = 100dr[2:0] = 101 dr[2:0] = 110 g028 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 normalized frequency (f / f ) in dr gain (db) 1 2 0 3 4 5 0.5 4.5 3.5 2.5 1.5 0 0.5 1 1.5 2 2.5 3 - - - - - - normalized frequency (f / f ) in dr gain (db) 0.05 0.1 0 0.15 0.35 0.2 0.25 0.3
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 figure 29. transfer function of on-chip decimation filters until 4 f mod for dr[2:0] = 000 and dr[2:0] = 110 reference figure 30 shows a simplified block diagram of the ads1299 internal reference. the 4.5-v reference voltage is generated with respect to avss. when using the internal voltage reference, connect vrefn to avss. (1) for v ref = 4.5 v: r1 = 9.8 k , r2 = 13.4 k , and r3 = 36.85 k . figure 30. internal reference the external band-limiting capacitors determine the amount of reference noise contribution. for high-end eeg systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 hz so that the reference noise does not dominate system noise. alternatively, the internal reference buffer can be powered down and vrefp can be applied externally. figure 31 shows a typical external reference drive circuitry. power-down is controlled by the pd_refbuf bit in the config3 register. this power-down is also used to share internal references when two devices are cascaded. by default, the device wakes up in external reference mode. copyright ? 2012, texas instruments incorporated submit documentation feedback 23 product folder link(s): ads1299 100 f m to adc reference inputs vcap1 10 f m vrefpvrefn bandgap 4.5 v avss r1 (1) r3 (1) r2 (1) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 normalized frequency (f in /f mod ) gain (db) g029
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com figure 31. external reference driver 24 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 100 w 100 k w 100 w opa211 10 pf 0.1 f m +5 v 0.1 f m 10 f m 100 f m 22 f m out vin +5 v trim 22 f m ref5025 to vrefp pin
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 clock the ads1299 provides two methods for device clocking: internal and external. internal clocking is ideally suited for low-power, battery-powered systems. the internal oscillator is trimmed for accuracy at room temperature. accuracy varies over the specified temperature range; see the electrical characteristics . clock selection is controlled by the clksel pin and the clk_en register bit. the clksel pin selects either the internal or external clock. the clk_en bit in the config1 register enables and disables the oscillator clock to be output in the clk pin. a truth table for these two pins is shown in table 6 . the clk_en bit is useful when multiple devices are used in a daisy-chain configuration. during power-down, the external clock is recommended be shut down to save power. table 6. clksel pin and clk_en bit config1.clk_en clksel pin bit clock source clk pin status 0 x external clock input: external clock 1 0 internal clock oscillator 3-state 1 1 internal clock oscillator output: internal clock oscillator data format the ads1299 outputs 24 bits of data per channel in binary twos complement format, msb first. the lsb has a weight of [v ref / (2 23 ? 1)]. a positive full-scale input produces an output code of 7fffffh and the negative full- scale input produces an output code of 800000h. the output clips at these codes for signals exceeding full-scale. table 7 summarizes the ideal output codes for different input signals. all 24 bits toggle when the analog input is at positive or negative full-scale. table 7. ideal output code versus input signal (1) input signal, v in (ainp ? ainn) ideal output code (2) v ref 7fffffh +v ref / (2 23 ? 1) 000001h 0 000000h ? v ref / (2 23 ? 1) ffffffh ? v ref (2 23 / 2 23 ? 1) 800000h (1) only valid for 24-bit resolution data rates. (2) excludes effects of noise, linearity, offset, and gain error. copyright ? 2012, texas instruments incorporated submit documentation feedback 25 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com spi interface the spi-compatible serial interface consists of four signals: cs, sclk, din, and dout. the interface reads conversion data, reads and writes registers, and controls ads1299 operation. the drdy output is used as a status signal to indicate when data are ready. drdy goes low when new data are available. chip select ( cs) chip select ( cs) selects the ads1299 for spi communication. cs must remain low for the entire serial communication duration. after the serial communication is finished, always wait four or more t clk cycles before taking cs high. when cs is taken high, the serial interface is reset, sclk and din are ignored, and dout enters a high-impedance state. drdy asserts when data conversion is complete, regardless of whether cs is high or low. serial clock (sclk) sclk is the serial peripheral interface (spi) serial clock. sclk shifts in commands and shifts out data from the device. sclk features a schmitt-triggered input and clocks data on the din and dout pins into and out of the ads1299. even though the input has hysteresis, it is recommended to keep sclk as clean as possible to prevent glitches from accidentally forcing a clock event. the absolute maximum sclk limit is specified in the serial interface timing table. when shifting in commands with sclk, make sure that the entire set of sclks is issued to the device. failure to do so can result in the device serial interface being placed into an unknown state, thus requiring cs to be taken high to recover. for a single device, the minimum speed required for sclk depends on the number of channels, number of bits of resolution, and output data rate. (for multiple cascaded devices, see the standard mode subsection of the multiple device configuration section.) for example, if the ads1299 is used in a 500-sps mode (8 channels, 24-bit resolution), the minimum sclk speed is 110 khz. data retrieval can be accomplished either by placing the device in rdatac mode or by issuing an rdata command for data on demand. the sclk rate limitation in equation 6 applies to rdatac. for the rdata command, the limitation applies if data must be read in between two consecutive drdy signals. equation 6 assumes that there are no other commands issued in between data captures. (6) data input (din) the data input pin (din) is used along with sclk to communicate with the ads1299 (opcode commands and register data). the device latches data on din on the sclk falling edge. 26 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 t < sclk t 4 t dr clk - n n + 24 bits channels
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 data output (dout) the data output pin (dout) is used with sclk to read conversion and register data from the ads1299. data on dout are shifted out on the sclk rising edge. dout goes to a high-impedance state when cs is high. in read data continuous mode (see the spi command definitions section for more details), the dout output line also indicates when new data are available. this feature can be used to minimize the number of connections between the device and system controller. figure 32 shows the ads1299 data output protocol. figure 32. spi bus data output data retrieval data retrieval can be accomplished in one of two methods. the read data continuous command (see the rdatac: read data continuous section) can be used to set the device in a mode to read data continuously without sending opcodes. the read data command (see the rdata: read data section) can be used to read just one data output from the device (see the spi command definitions section for more details). conversion data are read by shifting data out on dout. the msb of the data on dout is clocked out on the first sclk rising edge. drdy returns to high on the first sclk falling edge. din should remain low for the entire read operation. the number of bits in the data output depends on the number of channels and the number of bits per channel. for the ads1299, the number of data outputs is [(24 status bits + 24 bits 8 channels) = 216 bits]. the format of the 24 status bits is: (1100 + loff_statp + loff_statn + bits[4:7] of the gpio register). the data format for each channel data are twos complement and msb first. when channels are powered down using the user register setting, the corresponding channel output is set to '0'. however, the channel output sequence remains the same. the ads1299 also provides a multiple readback feature. data can be read out multiple times by simply giving more sclks, in which case the msb data byte repeats after reading the last byte. the daisy_en bit in the config1 register must be set to '1' for multiple readbacks. data ready ( drdy) drdy is an output. when drdy transitions low, new conversion data are ready. the cs signal has no effect on the data ready signal. drdy behavior is determined by whether the device is in rdatac mode or the rdata command is used to read data on demand. (see the rdatac: read data continuous and rdata: read data subsections of the spi command definitions section for further details). when reading data with the rdata command, the read operation can overlap the next drdy occurrence without data corruption. the start pin or the start command places the device either in normal data capture mode or pulse data capture mode. copyright ? 2012, texas instruments incorporated submit documentation feedback 27 product folder link(s): ads1299 cs sclk drdy dout stat 24-bit 24-bit 24-bit 24-bit 24-bit 24-bit 24-bit 24-bit 24-bit ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 216 sclks din
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com figure 33 shows the relationship between drdy, dout, and sclk during data retrieval (in case of an ads1299 with a selected data rate that gives 24-bit resolution). dout is latched out at the sclk rising edge. drdy is pulled high at the sclk falling edge. note that drdy goes high on the first sclk falling edge, regardless of whether data are being retrieved from the device or a command is being sent through the din pin. figure 33. drdy with data retrieval ( cs = 0) gpio the ads1299 has a total of four general-purpose digital i/o (gpio) pins available in normal mode of operation. the digital i/o pins are individually configurable as either inputs or outputs through the gpioc bits register. the gpiod bits in the gpio register control the pin level. when reading the gpiod bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. when the gpio pin is configured as an input, a write to the corresponding gpiod bit has no effect. when configured as an output, a write to the gpiod bit sets the output value. if configured as inputs, these pins must be driven (do not float). the gpio pins are set as inputs after power-on or after a reset. figure 34 shows the gpio port structure. the pins should be shorted to dgnd if not used. figure 34. gpio port pin power-down ( pwdn) when pwdn is pulled low, all on-chip circuitry is powered down. to exit power-down mode, take the pwdn pin high. upon exiting from power-down mode, the internal oscillator and the reference require time to wake up. during power-down, the external clock is recommended to be shut down to save power. 28 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 drdy dout sclk bit 215 bit 214 bit 213 x gpio pin gpio data (read) gpio data (write) gpio control
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 reset ( reset) there are two methods to reset the ads1299: pull the reset pin low, or send the reset opcode command. when using the reset pin, take the pin low to force a reset. make sure to follow the minimum pulse width timing specifications before taking the reset pin back high. the reset command takes effect on the eighth sclk falling edge of the opcode command. on reset, 18 t clk cycles are required to complete initialization of the configuration registers to default states and start the conversion cycle. note that an internal reset is automatically issued to the digital filter whenever the config1 register is set to a new value with a wreg command. start the start pin must be set high or the start command sent to begin conversions. when start is low or if the start command has not been sent, the device does not issue a drdy signal (conversions are halted). when using the start opcode to control conversions, hold the start pin low. the ads1299 features two modes to control conversions: continuous mode and single-shot mode. the mode is selected by single_shot (bit 3 of the config4 register). in multiple device configurations, the start pin is used to synchronize devices (see the multiple device configuration subsection of the spi interface section for more details). settling time the settling time (t settle ) is the time required for the converter to output fully-settled data when the start signal is pulled high. when start is pulled high, drdy is also pulled high. the next drdy falling edge indicates that data are ready. figure 35 shows the timing diagram and table 8 shows the settling time for different data rates. the settling time depends on f clk and the decimation ratio (controlled by the dr[2:0] bits in the config1 register). table 7 shows the settling time as a function of t clk . note that when start is held high and there is a step change in the input signal, 3 t dr is required for the filter to settle to the new value. settled data are available on the fourth drdy pulse. figure 35. settling time table 8. settling time for different data rates dr[2:0] normal mode unit 000 521 t clk 001 1033 t clk 010 2057 t clk 011 4105 t clk 100 8201 t clk 101 16393 t clk 110 32777 t clk copyright ? 2012, texas instruments incorporated submit documentation feedback 29 product folder link(s): ads1299 start opcode start pin din 4 / f clk drdy or t dr t settle
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com continuous mode conversions begin when the start pin is taken high or when the start opcode command is sent. as seen in figure 36 , the drdy output goes high when conversions are started and goes low when data are ready. conversions continue indefinitely until the start pin is taken low or the stop opcode command is transmitted. when the start pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. figure 37 and table 9 show the required drdy timing to the start pin and the start and stop opcode commands when controlling conversions in this mode. to keep the converter running continuously, the start pin can be permanently tied high. note that when switching from pulse mode to continuous mode, the start signal is pulsed or a stop command must be issued followed by a start command. this conversion mode is ideal for applications that require a fixed continuous stream of conversions results. (1) start and stop opcode commands take effect on the seventh sclk falling edge. figure 36. continuous conversion mode (1) start and stop commands take effect on the seventh sclk falling edge at the end of the opcode transmission. figure 37. start to drdy timing table 9. timing characteristics for figure 37 (1) symbol description min unit start pin low or stop opcode to drdy setup time to halt further t sdsu 16 1/f clk conversions t dshd start pin low or stop opcode to complete current conversion 16 1/f clk (1) start and stop commands take effect on the seventh sclk falling edge at the end of the opcode transmission. 30 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 t sdsu t dshd stop opcode drdy and dout start pin or stop (1) stop (1) start opcode (1) s rt pin ta din t dr t settle drdy stop opcode (1) or or
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 single-shot mode single-shot mode is enabled by setting the single_shot bit in the config4 register to '1'. in single-shot mode, the ads1299 performs a single conversion when the start pin is taken high or when the start opcode command is sent. as seen in figure 38 , when a conversion is complete, drdy goes low and further conversions are stopped. regardless of whether the conversion data are read or not, drdy remains low. to begin a new conversion, take the start pin low and then back high, or transmit the start opcode again. note that when switching from continuous mode to pulse mode, make sure the start signal is pulsed or issue a stop command followed by a start command. figure 38. drdy with no data retrieval in single-shot mode this conversion mode is provided for applications that require non-standard or non-continuous data rates. issuing a start command or toggling the start pin high resets the digital filter, effectively dropping the data rate by a factor of four. this mode leaves the system more susceptible to aliasing effects, requiring more complex analog or digital filtering. loading on the host processor increases because the processor must toggle the start pin or send a start command to initiate a new conversion cycle. multiple device configuration the ads1299 is designed to provide configuration flexibility when multiple devices are used in a system. the serial interface typically needs four signals: din, dout, sclk, and cs. with one additional chip select signal per device, multiple devices can be connected together. the number of signals needed to interface n devices is 3 + n . the bias drive amplifiers can be daisy-chained, as explained in the bias configuration with multiple devices subsection of the eeg-specific functions section. to use the internal oscillator in a daisy-chain configuration, one device must be set as the master for the clock source with the internal oscillator enabled (clksel pin = 1) and the internal oscillator clock brought out of the device by setting the clk_en register bit to '1'. this master device clock is used as the external clock source for other devices. copyright ? 2012, texas instruments incorporated submit documentation feedback 31 product folder link(s): ads1299 start drdy 4 / f clk 4 / f clk data updating t settle
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com when using multiple devices, the devices can be synchronized with the start signal. the delay from start to the drdy signal is fixed for a fixed data rate (see the start subsection of the spi interface section for more details on the settling times). figure 39 shows the behavior of two devices when synchronized with the start signal. there are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and daisy-chain mode. figure 39. synchronizing multiple converters 32 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 start 1 device 1 clk drdy drdy 1 start clk start 2 device 2 clk drdy drdy 2 start clk drdy 1 drdy 2
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 standard mode figure 40 a shows a configuration with two devices cascaded together. together, the devices create a system with 16 channels. dout, sclk, and din are shared. each device has its own chip select. when a device is not selected by the corresponding cs being driven to logic 1, the dout of this device is high-impedance. this structure allows the other device to take control of the dout bus. this configuration method is suitable for the majority of applications. daisy-chain mode daisy-chain mode is enabled by setting the daisy_en bit in the config1 register. figure 40 b shows the daisy- chain configuration. in this mode sclk, din, and cs are shared across multiple devices. the dout of one device is hooked up to the daisy_in of the other device, thereby creating a chain. also, when using daisy-chain mode, the multiple readback feature is not available. short the daisy_in pin to digital ground if not used. figure 2 describes the required timing for the device shown in the configurations of figure 40 . data from the ads1299 appear first on dout, followed by the status and data words. (1) to reduce pin count, set the start pin low and use the start serial command to synchronize and start conversions. figure 40. multiple device configurations copyright ? 2012, texas instruments incorporated submit documentation feedback 33 product folder link(s): ads1299 start drdy cs sclk din dout device 1 start drdy cs sclk din dout device 2 start (1) a) standard configuration clkclk int gpo0 gpo1 sclkmosi host processor miso clk start drdy cs sclk din dout 0 device 1 start drdy cs sclk din daisy_in 1 device 2 start (1) b) daisy-chain configuration clkclk int gpo sclkmosi host processor miso clk 0 dout 1 daisy_in 0
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com when all devices in the chain operate in the same register setting, din can be shared as well. this configuration reduces the spi communication signals to four, regardless of the number of devices. however, because the individual devices cannot be programmed, the bias driver cannot be shared among the multiple devices. furthermore, an external clock must be used. note that from figure 2 , the sclk rising edge shifts data out of the ads1299 on dout. the sclk rising edge is also used to latch data into the device daisy_in pin down the chain. this architecture allows for a faster sclk rate speed, but also makes the interface sensitive to board-level signal delays. the more devices in the chain, the more challenging it could become to adhere to setup and hold times. a star-pattern connection of sclk to all devices, minimizing dout length, and other printed circuit board (pcb) layout techniques helps. placing delay circuits (such as buffers) between dout and daisy_in are ways to mitigate this challenge. one other option is to insert a d flip-flop between dout and daisy_in clocked on an inverted sclk. note also that daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries. figure 41 shows a timing diagram for this mode. figure 41. daisy-chain timing the maximum number of devices that can be daisy-chained depends on the data rate at which the device is operated at. the maximum number of devices can be approximately calculated with equation 7 . where: n bits = device resolution (depending on data rate), and n channels = number of channels in the device. (7) for example, when the ads1299 is operated at a 2-ksps data rate with a 4-mhz f sclk , 10 devices can be daisy- chained. 34 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 f sclk f (n )(n dr bits channels ) + 24 n = devices dout daisy_in 10 do tu 0 sclk msb 1 msb 0 2 1 3 216 217 218 msb 1 lsb 0 lsb 1 219 337 lsb 1 da a ft rom d ce 1 evi da a ft rom vide ce 2
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 spi command definitions the ads1299 provides flexible configuration control. the opcode commands, summarized in table 10 , control and configure device operation. the opcode commands are stand-alone, except for the register read and write operations that require a second command byte plus data. cs can be taken high or held low between opcode commands but must stay low for the entire command operation (especially for multi-byte commands). system opcode commands and the rdata command are decoded by the ads1299 on the seventh sclk falling edge. the register read and write opcodes are decoded on the eighth sclk falling edge. be sure to follow spi timing requirements when pulling cs high after issuing a command. table 10. command definitions command description first byte second byte system commands wakeup wake-up from standby mode 0000 0010 (02h) standby enter standby mode 0000 0100 (04h) reset reset the device 0000 0110 (06h) start start and restart (synchronize) conversions 0000 1000 (08h) stop stop conversion 0000 1010 (0ah) data read commands enable read data continuous mode. rdatac 0001 0000 (10h) this mode is the default mode at power-up. (1) sdatac stop read data continuously mode 0001 0001 (11h) rdata read data by command; supports multiple read back. 0001 0010 (12h) register read commands rreg read n nnnn registers starting at address r rrrr 001 r rrrr (2xh) (2) 000 n nnnn (2) wreg write n nnnn registers starting at address r rrrr 010 r rrrr (4xh) (2) 000 n nnnn (2) (1) when in rdatac mode, the rreg command is ignored. (2) n nnnn = number of registers to be read or written ? 1. for example, to read or write three registers, set n nnnn = 0 (0010). r rrrr = starting register address for read or write opcodes. wakeup: exit standby mode this opcode exits low-power standby mode; see the standby: enter standby mode subsection of the spi command definitions section. time is required when exiting standby mode (see the electrical characteristics for details). there are no sclk rate restrictions for this command and it can be issued at any time. any following commands must be sent after a delay of 4 t clk cycles. standby: enter standby mode this opcode command enters low-power standby mode. all parts of the circuit are shut down except for the reference section. the standby mode power consumption is specified in the electrical characteristics . there are no sclk rate restrictions for this command and it can be issued at any time. do not send any other commands other than the wakeup command after the device enters standby mode. reset: reset registers to default values this command resets the digital filter cycle and returns all register settings to default values. see the reset (reset) subsection of the spi interface section for more details. there are no sclk rate restrictions for this command and it can be issued at any time. 18 t clk cycles are required to execute the reset command. avoid sending any commands during this time. start: start conversions this opcode starts data conversions. tie the start pin low to control conversions by command. if conversions are in progress, this command has no effect. the stop opcode command stops conversions. if the start command is immediately followed by a stop command, then there must be a 4-t clk cycle delay between them. when the start opcode is sent to the device, keep the start pin low until the stop command is issued. (see the start subsection of the spi interface section for more details.) there are no sclk rate restrictions for this command and it can be issued at any time. copyright ? 2012, texas instruments incorporated submit documentation feedback 35 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com stop: stop conversions this opcode stops conversions. tie the start pin low to control conversions by command. when the stop command is sent, the conversion in progress completes and further conversions are stopped. if conversions are already stopped, this command has no effect. there are no sclk rate restrictions for this command and it can be issued at any time. rdatac: read data continuous this opcode enables conversion data output on each drdy without the need to issue subsequent read data opcodes. this mode places the conversion data in the output register and may be shifted out directly. the read data continuous mode is the device default mode; the ads1299 defaults to this mode on power-up. rdatac mode is cancelled by the stop read data continuous command. if the device is in rdatac mode, a sdatac command must be issued before any other commands can be sent to the device. there are no sclk rate restrictions for this command. however, subsequent data retrieval sclks or the sdatac opcode command should wait at least 4 t clk cycles. rdatac timing is shown in figure 42 . as figure 42 shows, there is a keep out zone of 4 t clk cycles around the drdy pulse where this command cannot be issued in. if no data are retrieved from the device, dout and drdy behave similarly in this mode. to retrieve data from the device after the rdatac command is issued, make sure either the start pin is high or the start command is issued. figure 42 shows the recommended way to use the rdatac command. rdatac is ideally-suited for applications such as data loggers or recorders, where registers are set one time and do not need to be reconfigured. (1) t update = 4 / f clk . do not read data during this time. figure 42. rdatac usage 36 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 start drdy cs sclk din t update dout hi-z rdatac opcode status register + 8-channel data (216 bits) next data
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 sdatac: stop read data continuous this opcode cancels the read data continuous mode. there are no sclk rate restrictions for this command, but the next command must wait for 4 t clk cycles. rdata: read data issue this command after drdy goes low to read the conversion result (in stop read data continuous mode). there are no sclk rate restrictions for this command, and there is no wait time needed for the subsequent commands or data retrieval sclks. to retrieve data from the device after the rdata command is issued, make sure either the start pin is high or the start command is issued. when reading data with the rdata command, the read operation can overlap the next drdy occurrence without data corruption. figure 43 shows the recommended way to use the rdata command. rdata is best suited for ecg- and eeg-type systems, where register settings must be read or changed often between conversion cycles. figure 43. rdata usage sending multi-byte commands the ads1299 serial interface decodes commands in bytes and requires 4 t clk cycles to decode and execute. therefore, when sending multi-byte commands, a 4 t clk period must separate the end of one byte (or opcode) and the next. assuming clk is 2.048 mhz, then t sdecode (4 t clk ) is 1.96 s. when sclk is 16 mhz, one byte can be transferred in 500 ns. this byte transfer time does not meet the t sdecode specification; therefore, a delay must be inserted so the end of the second byte arrives 1.46 s later. if sclk is 4 mhz, one byte is transferred in 2 s. because this transfer time exceeds the t sdecode specification, the processor can send subsequent bytes without delay. in this later scenario, the serial port can be programmed to move from single-byte transfers per cycle to multiple bytes. copyright ? 2012, texas instruments incorporated submit documentation feedback 37 product folder link(s): ads1299 hi-z start drdy cs sclk din dout rdata opcode status register+ 8-channel data (216 bits) rdata opcode
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com rreg: read from register this opcode reads register data. the register read command is a two-byte opcode followed by the register data output. the first byte contains the command opcode and register address. the second opcode byte specifies the number of registers to read ? 1. first opcode byte: 001 r rrrr , where r rrrr is the starting register address. second opcode byte: 000 n nnnn , where n nnnn is the number of registers to read ? 1. the 17th sclk rising edge of the operation clocks out the msb of the first register, as shown in figure 44 . when the device is in read data continuous mode, an sdatac command must be issued before the rreg command can be issued. the rreg command can be issued any time. however, because this command is a multi-byte command, there are sclk rate restrictions depending on how the sclks are issued. see the serial clock (sclk) subsection of the spi interface section for more details. note that cs must be low for the entire command. figure 44. rreg command example: read two registers starting from register 00h (id register) (opcode 1 = 0010 0000, opcode 2 = 0000 0001) wreg: write to register this opcode writes register data. the register write command is a two-byte opcode followed by the register data input. the first byte contains the command opcode and register address. the second opcode byte specifies the number of registers to write ? 1. first opcode byte: 010 r rrrr , where r rrrr is the starting register address. second opcode byte: 000 n nnnn , where n nnnn is the number of registers to write ? 1. after the opcode bytes, the register data follows (in msb-first format), as shown in figure 45 . the wreg command can be issued any time. however, because this command is a multi-byte command, there are sclk rate restrictions depending on how the sclks are issued. see the serial clock (sclk) subsection of the spi interface section for more details. note that cs must be low for the entire command. figure 45. wreg command example: write two registers starting from 00h (id register) (opcode 1 = 0100 0000, opcode 2 = 0000 0001) 38 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 1 9 17 25 cs sclk din opcode 1 opcode 2 reg data 1 reg data 2 dout 1 9 17 25 cs sclk din opcode 1 opcode 2 dout reg data reg data + 1
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 register map table 11 describes the various ads1299 registers. table 11. register assignments reset value address register (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device settings (read-only registers) 00h id 00 rev_id3 rev_id2 rev_id1 1 dev_id2 dev_id1 nu_ch2 nu_ch1 global settings across channels 01h config1 96 1 daisy_en clk_en 1 0 dr2 dr1 dr0 02h config2 c0 1 1 0 int_cal 0 cal_amp0 cal_freq1 cal_freq0 bias_loff_ 03h config3 60 pd_refbuf 1 1 bias_meas biasref_int pd_bias bias_stat sens 04h loff 00 comp_th2 comp_th1 comp_th0 0 ilead_off1 ilead_off0 flead_off1 flead_off0 channel-specific settings 05h ch1set 61 pd1 gain12 gain11 gain10 srb2 mux12 mux11 mux10 06h ch2set 61 pd2 gain22 gain21 gain20 srb2 mux22 mux21 mux20 07h ch3set 61 pd3 gain32 gain31 gain30 srb2 mux32 mux31 mux30 08h ch4set 61 pd4 gain42 gain41 gain40 srb2 mux42 mux41 mux40 09h ch5set 61 pd5 gain52 gain51 gain50 srb2 mux52 mux51 mux50 0ah ch6set 61 pd6 gain62 gain61 gain60 srb2 mux62 mux61 mux60 0bh ch7set 61 pd7 gain72 gain71 gain70 srb2 mux72 mux71 mux70 0ch ch8set 61 pd8 gain82 gain81 gain80 srb2 mux82 mux81 mux80 0dh bias_sensp 00 biasp8 biasp7 biasp6 biasp5 biasp4 biasp3 biasp2 biasp1 0eh bias_sensn 00 biasn8 biasn7 biasn6 biasn5 biasn4 biasn3 biasn2 biasn1 0fh loff_sensp 00 loffp8 loffp7 loffp6 loffp5 loffp4 loffp3 loffp2 loffp1 10h loff_sensn 00 loffm8 loffm7 loffm6 loffm5 loffm4 loffm3 loffm2 loffm1 11h loff_flip 00 loff_flip8 loff_flip7 loff_flip6 loff_flip5 loff_flip4 loff_flip3 loff_flip2 loff_flip1 lead-off status registers (read-only registers) 12h loff_statp 00 in8p_off in7p_off in6p_off in5p_off in4p_off in3p_off in2p_off in1p_off 13h loff_statn 00 in8m_off in7m_off in6m_off in5m_off in4m_off in3m_off in2m_off in1m_off gpio and other registers 14h gpio 0f gpiod4 gpiod3 gpiod2 gpiod1 gpioc4 gpioc3 gpioc2 gpioc1 15h misc1 00 0 0 srb1 0 0 0 0 0 16h misc2 00 0 0 0 0 0 0 0 0 single_ pd_loff_ 17h config4 00 0 0 0 0 0 0 shot comp copyright ? 2012, texas instruments incorporated submit documentation feedback 39 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com user register description id: id control register (factory-programmed, read-only) address = 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev_id3 rev_id2 rev_id1 1 dev_id2 dev_id1 nu_ch2 nu_ch1 this register is programmed during device manufacture to indicate device characteristics. bits[7:5] not used bit 4 must be set to '1' bits[3:0] factory-programmed device identification bits 1110 = ads1299 config1: configuration register 1 address = 01h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 daisy_en clk_en 1 0 dr2 dr1 dr0 this register configures the daisy_en bit, clock, and data rate. bit 7 must be set to '1' bit 6 daisy_en: daisy-chain and multiple readback mode this bit determines which mode is enabled. 0 = daisy-chain mode (default) 1 = multiple readback mode bit 5 clk_en: clk connection (1) this bit determines if the internal oscillator signal is connected to the clk pin when the clksel pin = 1. 0 = oscillator clock output disabled (default) 1 = oscillator clock output enabled bits[4:3] must always be set to '10' bits[2:0] dr[2:0]: output data rate f mod = f clk / 2. these bits determine the output data rate of the device. (1) additional power is consumed when driving external devices. bit data rate sample rate (1) 000 f mod / 64 16 ksps 001 f mod / 128 8 ksps 010 f mod / 256 4 ksps 011 f mod / 512 2 ksps 100 f mod / 1024 1 ksps 101 f mod / 2048 500 sps 110 (default) f mod / 4096 250 sps 111 do not use n/a (1) f clk = 2.048 mhz. 40 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 config2: configuration register 2 address = 02h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 0 int_cal 0 cal_amp0 cal_freq1 cal_freq0 this register configures the test signal generation. see the input multiplexer section for more details. bits[7:5] must always be set to '110' bit 4 int_cal: test source this bit determines the source for the test signal. 0 = test signals are driven externally (default) 1 = test signals are generated internally bit 3 must always be set to '0' bit 2 cal_amp0: test signal amplitude this bit determines the calibration signal amplitude. 0 = 1 (vrefp ? vrefn) / 2.4 mv (default) 1 = 2 (vrefp ? vrefn) / 2.4 mv bits[1:0] cal_freq[1:0]: test signal frequency these bits determine the calibration signal frequency. 00 = pulsed at f clk / 2 21 (default) 01 = pulsed at f clk / 2 20 10 = not used 11 = at dc copyright ? 2012, texas instruments incorporated submit documentation feedback 41 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com config3: configuration register 3 address = 03h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pd_refbuf 1 1 bias_meas biasref_int pd_bias bias_loff_sens bias_stat this register configures multi-reference and bias operations. bit 7 pd_refbuf: power-down reference buffer this bit determines the power-down reference buffer state. 0 = power-down internal reference buffer (default) 1 = internal reference buffer enabled bits[6:5] must always be set to '1' bit 4 bias_meas: bias measurement this bit enables bias measurement. the bias signal may be measured with any channel. 0 = open (default) 1 = biasin signal is routed to the channel that has the mux_setting 010 (v ref ) bit 3 biasref_int: biasref signal this bit determines the biasref signal source. 0 = biasref signal fed externally (default) 1 = biasref signal (avdd ? avss) / 2 generated internally bit 2 pd_bias: bias buffer power this bit determines the bias buffer power state. 0 = bias buffer is powered down (default) 1 = bias buffer is enabled bit 1 bias_loff_sens: bias sense function this bit enables the bias sense function. 0 = bias sense is disabled (default) 1 = bias sense is enabled bit 0 bias_stat: bias lead-off status this bit determines the bias status. 0 = bias is connected (default) 1 = bias is not connected 42 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 loff: lead-off control register address = 04h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comp_th2 comp_th1 comp_th0 0 ilead_off1 ilead_off0 flead_off1 flead_off0 this register configures the lead-off detection operation. bits[7:5] comp_th[2:0]: lead-off comparator threshold these bits determine the lead-off comparator threshold level setting. see the lead-off detection subsection of the eeg- specific functions section for a detailed description. comparator positive side 000 = 95% (default) 001 = 92.5% 010 = 90% 011 = 87.5% 100 = 85% 101 = 80% 110 = 75% 111 = 70% comparator negative side 000 = 5% (default) 001 = 7.5% 010 = 10% 011 = 12.5% 100 = 15% 101 = 20% 110 = 25% 111 = 30% bit 4 must always be set to '0' bits[3:2] ilead_off[1:0]: lead-off current magnitude these bits determine the magnitude of current for the current lead-off mode. 00 = 6 na (default) 01 = 24 na 10 = 6 a 11 = 24 a bits[1:0] flead_off[1:0]: lead-off frequency these bits determine the frequency of lead-off detect for each channel. 00 = dc lead-off detection (default) 01 = ac lead-off detection at 7.8 hz (sys_clk / 2 18 ) 10 = ac lead-off detection at 31.2 hz (sys_clk / 2 16 ) 11 = ac lead-off detection at f dr / 4 copyright ? 2012, texas instruments incorporated submit documentation feedback 43 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com chnset: individual channel settings (n = 1:8) address = 05h to 0ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pd1 gain12 gain11 gain10 srb2 mux12 mux11 mux10 this register configures the power mode, pga gain, and multiplexer settings channels. see the input multiplexer section for details. ch[2:8]set are similar to ch1set, corresponding to the respective channels. bit 7 pd: power-down this bit determines the channel power mode for the corresponding channel. 0 = normal operation (default) 1 = channel power-down bits[6:4] gain[2:0]: pga gain these bits determine the pga gain setting. 000 = 1 001 = 2 010 = 4 011 = 6 100 = 8 101 = 12 110 = 24 (default) 111 = n/a bit 3 srb2: source, reference bias channel this bit determines the srb2 connection for the corresponding channel. 0 = open (off) (default) 1 = closed (on) bits[2:0] muxn[2:0]: channel input these bits determine the channel input selection. 000 = normal electrode input (default) 001 = input shorted (for offset or noise measurements) 010 = used in conjunction with bias_meas bit for bias measurements. see the bias drive (dc bias circuit) subsection of the eeg-specific functions section for more details. 011 = mvdd for supply measurement 100 = temperature sensor 101 = test signal 110 = bias_drp (positive electrode is the driver) 111 = bias_drn (negative electrode is the driver) bias_sensp: bias drive positive sense selection address = 0dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 biasp8 biasp7 biasp6 biasp5 biasp4 biasp3 biasp2 biasp1 this register controls the selection of positive signals from each channel for bias drive derivation. see the bias drive (dc bias circuit) subsection of the eeg-specific functions section for details. bias_sensn: bias drive negative sense selection address = 0eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 biasn8 biasn7 biasn6 biasn5 biasn4 biasn3 biasn2 biasn1 this register controls the selection of negative signals from each channel for bias drive derivation. see the bias drive (dc bias circuit) subsection of the eeg-specific functions section for details. 44 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 loff_sensp: lead off positive sense selection address = 0fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loffp8 loffp7 loffp6 loffp5 loffp4 loffp3 loffp2 loffp1 this register selects the positive side from each channel for lead-off detection. see the lead-off detection subsection of the eeg-specific functions section for details. note that the loff_statp register bits are only valid if the corresponding loff_sensp bits are set to '1'. loff_sensn: lead off negative sense selection address = 10h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loffm8 loffm7 loffm6 loffm5 loffm4 loffm3 loffm2 loffm1 this register selects the negative side from each channel for lead-off detection. see the lead-off detection subsection of the eeg-specific functions section for details. note that the loff_statn register bits are only valid if the corresponding loff_sensn bits are set to '1'. loff_flip: lead off current direction control address = 11h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loff_flip8 loff_flip7 loff_flip6 loff_flip5 loff_flip4 loff_flip3 loff_flip2 loff_flip1 this register controls the current direction used for lead-off derivation. see the lead-off detection subsection of the eeg-specific functions section for details. loff_statp: lead-off positive input status address = 12h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 in8p_off in7p_off in6p_off in5p_off in4p_off in3p_off in2p_off in1p_off this register stores the status of whether the positive electrode on each channel is on or off. see the lead-off detection subsection of the eeg-specific functions section for details. ignore the loff_statp values if the corresponding loff_sensp bits are not set to '1'. '0' is lead-on (default) and '1' is lead-off. when the loff_sensp bits are '0', the loff_statp bits should be ignored. loff_statn: lead-off negative input status address = 13h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 in8m_off in7m_off in6m_off in5m_off in4m_off in3m_off in2m_off in1m_off this register stores the status of whether the negative electrode on each channel is on or off. see the lead-off detection subsection of the eeg-specific functions section for details. ignore the loff_statn values if the corresponding loff_sensn bits are not set to '1'. '0' is lead-on (default) and '1' is lead-off. when the loff_sensn bits are '0', the loff_statp bits should be ignored. copyright ? 2012, texas instruments incorporated submit documentation feedback 45 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com gpio: general-purpose i/o register address = 14h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpiod4 gpiod3 gpiod2 gpiod1 gpioc4 gpioc3 gpioc2 gpioc1 this register controls the action of the four gpio pins. bits[7:4] gpiod[4:1]: gpio data these bits are used to read and write data to the gpio ports. when reading the register, the data returned correspond to the state of the gpio external pins, whether they are programmed as inputs or as outputs. as outputs, a write to the gpiod sets the output value. as inputs, a write to the gpiod has no effect. bits[3:0] gpioc[4:1]: gpio control (corresponding gpiod) these bits determine if the corresponding gpiod pin is an input or output. 0 = output 1 = input (default) misc1: miscellaneous 1 address = 15h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 srb1 0 0 0 0 0 this register is for miscellaneous use. bits[7:6] must always be set to '0' bit 5 srb1: stimulus, reference, and bias 1 this bit connects the srb1 to all eight channels inverting inputs. 0 = switches open (default) 1 = switches closed bits[4:0] must always be set to '0' misc2: miscellaneous 2 address = 16h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 0 0 this register is for miscellaneous use. bits[7:0] must always be set to '0' 46 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 config4: configuration register 4 address = 17h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 single_shot 0 pd_loff_comp 0 bits[7:4] must always be set to '0' bit 3 single_shot: single-shot conversion this bit sets the conversion mode. 0 = continuous conversion mode (default) 1 = single-shot mode bit 2 must always be set to '0' bit 1 pd_loff_comp: lead-off comparator power-down this bit powers down the lead-off comparators. 0 = lead-off comparators disabled (default) 1 = lead-off comparators enabled bit 0 must always be set to '0' copyright ? 2012, texas instruments incorporated submit documentation feedback 47 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com eeg-specific functions input multiplexer (rerouting the bias drive signal) the input multiplexer has eeg-specific functions for the bias drive signal. the bias signal is available at the biasout pin when the appropriate channels are selected for bias derivation, feedback elements are installed external to the chip, and the loop is closed. this signal can either be fed after filtering or fed directly into the biasin pin, as shown in figure 46 . this biasin signal can be multiplexed into any input electrode by setting the mux bits of the appropriate channel set registers to '110' for p-side or '111' for n-side. figure 46 shows the bias signal generated from channels 1, 2, and 3 and routed to the n-side of channel 8. this feature can be used to dynamically change the electrode that is used as the reference signal to drive the patient body. (1) typical values for example only. figure 46. example of biasout signal configured to be routed to in8n 48 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 mux1[2:0] = 000 bias_sensp[0] = 1 bias_sensn[0] = 1 mux2[2:0] = 000 mux3[2:0] = 000 mux8[2:0] = 111 low-noise pga1 bias_sensp[1] = 1 bias_sensn[1] = 1 low-noise pga2 bias_sensp[2] = 1 bias_sensn[2] = 1 low-noise pga3 bias_amp bias_sensp[7] = 0 bias_sensn[7] = 0 low-noise pga8 biasout biasinv biasref biasin filter or feedthrough device ? ? mux in1p ? in1n in2pin3p in8p in2nin3n in8n 1 m w (1) 1.5 nf (1) (avdd + avss) 2 biasref_int = 1 biasref_int = 0
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 input multiplexer (measuring the bias drive signal) also, the biasout signal can be routed to a channel (that is not used for the calculation of bias) for measurement. figure 47 shows the register settings to route the biasin signal to channel 8. the measurement is done with respect to the voltage on the biasref pin. if biasref is chosen to be internal, it would be at [(avdd + avss) / 2]. this feature is useful for debugging purposes during product development. (1) typical values for example only. figure 47. biasout signal configured to be read back by channel 8 copyright ? 2012, texas instruments incorporated submit documentation feedback 49 product folder link(s): ads1299 mux1[2:0] = 000 bias_sensp[0] = 1 bias_sensn[0] = 1 mux2[2:0] = 000 mux3[2:0] = 000 mux8[2:0] = 010 bias_meas = 1 and low-noise pga1 bias_sensp[1] = 1 bias_sensn[1] = 1 low-noise pga2 bias_sensp[2] = 1 bias_sensn[2] = 1 low-noise pga3 bias_amp bias_sensp[7] = 0 bias_sensn[7] = 0 low-noise pga8 biasout biasinv biasref biasin filter or feedthrough device ? ? in1p in1n mux ? in2nin3n in8n in2pin3p in8p mux8[2:0] = 111 1 m w (1) 1.5 nf (1) biasref_int = 1 biasref_int = 0 (avdd + avss) 2
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com lead-off detection patient electrode impedances are known to decay over time. these electrode connections must be continuously monitored to verify that a suitable connection is present. the ads1299 lead-off detection functional block provides significant flexibility to the user to choose from various lead-off detection strategies. though called lead- off detection, this is in fact an electrode-off detection. the basic principle is to inject an excitation signal and measure the response to determine if the electrode is off. as shown in the lead-off detection functional block diagram in figure 48 , this circuit provides two different methods of determining the state of the patient electrode. the methods differ in the frequency content of the excitation signal. lead-off can be selectively done on a per channel basis using the loff_sensp and loff_sensn registers. also, the internal excitation circuitry can be disabled and just the sensing circuitry can be enabled. figure 48. lead-off detection 50 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 51 k w 51 k w z 1 47 nf z 2 47 nf skin, electrode contact model patient protection resistor avdd loff_sensp avss loff_sensn to adc v inp v inn patient flead_off[0:1] 6 na and 24 na 6 a and 24 a m m 51 k w z 3 47 nf bias out
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 dc lead-off in this method, the lead-off excitation is with a dc signal. the dc excitation signal can be chosen from either an external pull-up or pull-down resistor or an internal current source or sink, as shown in figure 49 . one side of the channel is pulled to supply and the other side is pulled to ground. the pull-up and pull-down current can be swapped (as shown in figure 49 b and figure 49 c) by setting the bits in the loff_flip register. in case of a current source or sink, the magnitude of the current can be set by using the ilead_off[1:0] bits in the loff register. the current source or sink gives larger input impedance compared to the 10-m ? pull-up or pull-down resistor. figure 49. dc lead-off excitation options sensing of the response can be done either by searching the digital output code from the device or by monitoring the input voltages with an on-chip comparator. if either electrode is off, the pull-up and pull-down resistors saturate the channel. searching the output code determines if either the p-side or the n-side is off. to pinpoint which one is off, the comparators must be used. the input voltage is also monitored using a comparator and a 3- bit dac whose levels are set by the comp_th[2:0] bits in the loff register. the output of the comparators are stored in the loff_statp and loff_statn registers. these registers are available as a part of the output data stream. (see the data output (dout) subsection of the spi interface section.) if dc lead-off is not used, the lead-off comparators can be powered down by setting the pd_loff_comp bit in the config4 register. an example procedure to turn on dc lead-off is given in the lead-off subsection of the quick-start guide section. ac lead-off (one time or periodic) in this method, an in-band ac signal is used for excitation. the ac signal is generated by alternatively providing a current source and sink at the input with a fixed frequency. the frequency can be chosen by the flead_off[1:0] bits in the loff register. the excitation frequency is chosen to be one of the two in-band frequency selections (7.8 hz or 31.2 hz). this in-band excitation signal is passed through the channel and measured at the output. sensing of the ac signal is done by passing the signal through the channel to digitize it and measure at the output. the ac excitation signals are introduced at a frequency that is in the band of interest. the signal can be filtered out separately and processed. by measuring the magnitude of the excitation signal at the output spectrum, the electrode impedance can be calculated. for continuous lead-off, an out-of-band ac current source or sink must be externally applied to the inputs. this signal can then be digitally post processed to determine the electrode impedance. copyright ? 2012, texas instruments incorporated submit documentation feedback 51 product folder link(s): ads1299 a) external pull-up or pull-down resistors b) input current source (loff_flip = 0) low-noise pgan 10 m w 10 m w avdd inp inn device avdd inp inn device low-noise pgan c) input current source (loff_flip = 1) avdd inp inn device low-noise pgan avss
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com bias lead-off the ads1299 provides two modes for determining whether the bias is correctly connected: ? bias lead-off detection during normal operation ? bias lead-off detection during power-up the following sections provide details of the two modes of operation. bias lead-off detection during normal operation during normal operation, the ads1299 bias lead-off at power-up function cannot be used because it is necessary to power off the bias amplifier. bias lead off detection at power-up this feature is included in the ads1299 for use in determining whether the bias electrode is suitably connected. at power-up, the ads1299 provides two measurement procedures to determine the bias electrode connection status using either a current or an external pull-down resistor, as shown in figure 50 . the reference level of the comparator is set to determine the acceptable bias impedance threshold. figure 50. bias lead-off detection at power-up when the bias amplifier is powered on, the current source has no function. only the comparator can be used to sense the voltage at the output of the bias amplifier. the comparator thresholds are set by the same loff[7:5] bits used to set the thresholds for other negative inputs. 52 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 51 k w 47 nf skin, electrode contact model patient protection resistor bias_stat patient avss bias_sens to adc input (through v connection to any of the channels). ref ilgnd_off[1:0]
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 bias drive (dc bias circuit) the bias circuitry is used as a means to counter the common-mode interference in a eeg system as a result of power lines and other sources, including fluorescent lights. the bias circuit senses the common-mode of a selected set of electrodes and creates a negative feedback loop by driving the body with an inverted common- mode signal. the negative feedback loop restricts the common-mode movement to a narrow range, depending on the loop gain. stabilizing the entire loop is specific to the individual user system based on the various poles in the loop. the ads1299 integrates the muxes to select the channel and an operational amplifier. all amplifier terminals are available at the pins, allowing the user to choose the components for the feedback loop. the circuit in figure 52 illustrates the overall functional connectivity for the bias circuit. the reference voltage for the bias drive can be chosen to be internally generated [(avdd + avss) / 2] or it can be provided externally with a resistive divider. the selection of an internal versus external reference voltage for the bias loop is defined by writing the appropriate value to the biasref_int bit in the config2 register. if the bias function is not used, the amplifier can be powered down using the pd_bias bit (see the config3: configuration register 3 subsection of the register map section for details). this bit is also used in daisy-chain mode to power-down all but one of the bias amplifiers. the biasin pin functionality is explained in the input multiplexer section. an example procedure to use the bias amplifier is shown in the bias drive subsection of the quick-start guide section. bias configuration with multiple devices figure 51 shows multiple devices connected to the bias drive. figure 51. bias drive connection for multiple devices copyright ? 2012, texas instruments incorporated submit documentation feedback 53 product folder link(s): ads1299 biasinv bias out bias ref biasin va1-8 device 2 va1-8 biasinv bias out bias ref biasin va1-8 device n va1-8 power-down power-down biasinv bias out bias ref biasin va1-8 device 1 va1-8 to input mux to input mux to input mux
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com (1) typical values. figure 52. bias channel selection 54 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 220 k w 18.15 k w 18.15 k w bias1p 220 k w 3.3 k w bias1n 220 k w 18.15 k w 18.15 k w bias2p 3.3 k w 220 k w bias2n from mux1p from mux2p from mux2n from mux1n 220 k w 18.15 k w 18.15 k w bias3p 220 k w 3.3 k w bias3n 220 k w 18.15 k w 18.15 k w bias4p 3.3 k w 220 k w bias4n from mux3p from mux4p from mux4n from mux3n 220 k w 18.15 k w 18.15 k w bias5p 220 k w 3.3 k w bias5n 220 k w 18.15 k w 18.15 k w bias6p 3.3 k w 220 k w bias6n from mux5p from mux6p from mux6n (avdd + avss) / 2 biasout from mux5n 220 k w 18.15 k w 18.15 k w r (1) 1 m w ext c (1) 1.5 nf ext bias7p 220 k w 3.3 k w bias7n 220 k w 18.15 k w 18.15 k w bias8p 3.3 k w 220 k w bias8n biasref_int = 1 from mux7p from mux8p from mux8n from mux7n bias amp biasinv biasref biasref_int = 0 pga1ppga1n pga3p pga3n pga5p pga5n pga7p pga7n pga8n pga8p pga6n pga6p pga4n pga4p pga2n pga2p
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 quick-start guide pcb layout power supplies and grounding the ads1299 has three supplies: avdd, avdd1, and dvdd. both avdd and avdd1 should be as quiet as possible. avdd1 provides the supply to the charge pump block and has transients at f clk . therefore, avdd1 and avss1 are recommended to be star-connected to avdd and avss. it is important to eliminate noise from avdd and avdd1 that is non-synchronous with the ads1299 operation. each ads1299 supply should be bypassed with 10- f and a 0.1- f solid ceramic capacitors. placement of the digital circuits [(such as digital signal processors (dsps), microcontrollers, and field-programmable gate arrays (fpgas)] in the system is recommenced to done such that the return currents on those devices do not cross the analog return path of the ads1299. the ads1299 can be powered from unipolar or bipolar supplies. the capacitors used for decoupling can be surface-mount, low-cost, low-profile multi-layer ceramic capacitors. in most cases, the vcap1 capacitor can also be a multi-layer ceramic, but in systems where the board is subjected to high- or low-frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class 1 capacitor (for example, c0g or npo) be installed. eia class 2 and class 3 dielectrics (such as x7r, x5r, and x8r) are ferroelectric. the piezoelectric property of these capacitors can appear as electrical noise coming from the capacitor. when using internal reference, noise on the vcap1 node results in performance degradation. connecting the device to unipolar (+5 v and +3.3 v) supplies figure 53 illustrates the ads1299 connected to a unipolar supply. in this example, analog supply (avdd) is referenced to analog ground (avss) and digital supply (dvdd) is referenced to digital ground (dgnd). note: place the capacitors for supply, reference, and vcap1 to vcap4 as close to the package as possible. figure 53. single-supply operation copyright ? 2012, texas instruments incorporated submit documentation feedback 55 product folder link(s): ads1299 device avdd 0.1 f m 1 f m +5 v avdd1 avss avss1 dgnd dvdd +3.3 v 0.1 f m 1 f m 0.1 f m vrefp vrefn vcap1vcap2 vcap3 vcap4 1 f m 1 f m 1 f m 10 f m 100 f m 0.1 f m resv1
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com connecting the device to bipolar ( 2.5 v and 3.3 v) supplies figure 54 illustrates the ads1299 connected to a bipolar supply. in this example, the analog supplies connect to the device analog supply (avdd). this supply is referenced to the device analog return (avss), and the digital supply (dvdd) is referenced to the device digital ground return (dgnd). note: place the capacitors for supply, reference, and vcap1 to vcap4 as close to the package as possible. figure 54. bipolar supply operation shielding analog signal paths as with any precision circuit, careful pcb layout ensures the best performance. it is essential to make short, direct interconnections and avoid stray wiring capacitance ? particularly at the analog input pins and avss. these analog input pins are high-impedance and extremely sensitive to extraneous noise. the avss pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. leakage currents between the pcb traces can exceed the input bias current of the ads1299 if shielding is not implemented. digital signals should be kept as far as possible from the analog input signals on the pcb. 56 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 device 0.1 f m 1 f m avdd avdd1 0.1 f m 1 f m - 2.5 v avss avss1 dgnd dvdd +2.5 v +3.3 v 0.1 f m 1 f m vcap1 vcap2 vcap3 0.1 f m vrefp vrefn 10 f m vcap4 1 f m 1 f m 1 f m - 2.5 v 100 f m 0.1 f m resv1
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 power-up sequencing before device power-up, all digital and analog inputs must be low. at the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in figure 55 . at this time, begin supplying the master clock signal to the clk pin. wait for time t por , then transmit a reset pulse. after releasing reset, the configuration register must be programmed; see the config1: configuration register 1 subsection of the register map section for details. the power-up sequence timing is shown in table 12 . figure 55. power-up timing diagram table 12. power-up sequence timing symbol description min typ max unit t por wait after power-up until reset 2 16 t clk t rst reset low width 2 t clk setting the device for basic data capture this section outlines the procedure to configure the device in a basic state and capture data. this procedure is intended to put the device in a data sheet condition to check if the device is working properly in the user system. this procedure is recommended to be followed initially to get familiar with the device settings. when this procedure is verified, the device can be configured as needed. for details on the timings for commands, refer to the appropriate sections in the data sheet. also, some sample programming codes are added for the eeg- specific functions. copyright ? 2012, texas instruments incorporated submit documentation feedback 57 product folder link(s): ads1299 power supplies reset t rst start using the device t por 18 t clk
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com figure 56. initial flow at power-up 58 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299 set = 1 set = 1 wait f pdwn reset or 1 s for power-on reset // delay for power-on reset and oscillator start-up // if start is tied high, after this step // toggles at f / 8192 drdy clk set clksel pin = 1 and wait for oscillator to wake up no analog and digital power-up // follow power-up sequencing external clock set clksel pin = 0 and provide external clock f = 2.048 mhz clk yes set pdb_refbuf = 1 and wait for internal reference to settle write certain registers, including input short set start = 1 // activate conversion // after this point should toggle at // f / 8192 drdy clk // set device for dr = f / 4096 wreg config1 96h wreg config2 c0h // set all channels to input short wreg chnset 01h mod yes rdatac // put the device back in rdatac mode rdatac capture data and check noise // look for and issu s drdy e 24 + n 24 sclk set test signals capture data and test signal // activate a (1 mv v / 2. 4) square-wave test signal // on all channels sdatac wreg config2 d0h wreg chnset 05h rdatac ref // look for and issu s drdy e 24 + n 24 sclk external reference // if using internal reference, send this command ? wreg config3 e0h no send sdatac command // device wakes up in rdatac mode, so send // sdatac command so registers can be written sdatac issue reset pulse, wait for 18 t s clk // activate dut // can be either tied permanently low // or selectively pulled low before sending // commands or reading or sending data from or to the device cs
ads1299 www.ti.com sbas499a ? july 2012 ? revised august 2012 lead-off sample code to set dc lead-off with pull-up and pull-down resistors on all channels. wreg loff 00h // comparator threshold at 95% and 5%, pull-up or pull-down current source // dc lead-off wreg config4 02h // turn-on dc lead-off comparators wreg loff_sensp ffh // turn on the p-side of all channels for lead-off sensing wreg loff_sensn ffh // turn on the n-side of all channels for lead-off sensing observe the status bits of the output data stream to monitor lead-off status. bias drive sample code to choose bias as an average of the first three channels. wreg bias_sensp 07h // select channel 1 ? 3 p-side for bias sensing wreg bias_sensn 07h // select channel 1 ? 3 n-side for bias sensing wreg config3 b ? x11x 1100 // turn on bias amplifier, set internal biasref voltage sample code to route the biasout signal through channel 4 n-side and measure bias with channel 5. make sure the external side to the chip biasout is connected to biasin. wreg config3 b ? x111 1100 // turn on bias amplifier, set internal biasref voltage, set bias measurement bit wreg ch4set b ? xxxx 0111 // route biasin to channel 4 n-side wreg ch5set b ? xxxx 0010 // route biasin to be measured at channel 5 w.r.t biasref copyright ? 2012, texas instruments incorporated submit documentation feedback 59 product folder link(s): ads1299
ads1299 sbas499a ? july 2012 ? revised august 2012 www.ti.com revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (july 2012) to revision a page ? changed product column of family and ordering information table .................................................................................... 2 60 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder link(s): ads1299
package option addendum www.ti.com 8-aug-2012 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) ads1299ipag active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr ADS1299IPAGR active tqfp pag 64 1500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ADS1299IPAGR tqfp pag 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 package materials information www.ti.com 8-aug-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ADS1299IPAGR tqfp pag 64 1500 367.0 367.0 45.0 package materials information www.ti.com 8-aug-2012 pack materials-page 2
mechanical data mtqf006a january 1995 revised december 1996 post office box 655303 ? dallas, texas 75265 pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

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